1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate electrode to control an underlying surface channel joining a source and drain. The channel, source and drain are located in a semiconductor substrate, with the substrate being doped oppositely to the source and drain. The gate electrode is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a patterned gate electrode as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate electrode and the source/drain regions.
Polysilicon (also called polycrystaline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon as the gate electrode in place of aluminum. Since polysilicon has the same high melting point as a silicon substrate, it can be deposited prior to source and drain formation, and serve as a mask during introduction of the source and drain regions by ion implantation. The resistance of polysilicon can be further reduced by forming a silicide on its top surface.
There is a relentless trend to miniaturize semiconductor dimensions. The number of IGFETs that can be manufactured on an integrated circuit chip can be increased by decreasing the horizontal dimensions. Resolution refers to the horizontal linewidth or space that a lithographic system can adequately print or resolve. Lithographic systems include optical projection and step and repeat equipment, and electron beam lithography equipment. In optical systems, for instance, resolution is limited by the equipment (e.g., diffraction of light, lens aberrations, mechanical stability), optical properties of the photoresist (e.g., resolution, photosensitivity, index of refiaction), and process characteristics (e.g., softbake step, develop step, postbake step, and etching step).
The planarization of semiconductor wafers is becoming increasingly important as the number of layers used to form integrated circuits increases. For instance, the gate electrode and/or metallization layers formed to provide interconnects between various devices may result in nonuniform surfaces. The surface nonuniformities may interfere with the optical resolution of subsequent lithographic steps, leading to difficulty with printing high resolution patterns. The surface nonuniformities may also interfere with step coverage of subsequently deposited metal layers and possibly cause open circuits.
IGFETs are generally electrically isolated fiom one another in the substrate to prevent spurious channels from forming between them, and selected IGFETs are interconnected by an overlying metallization pattern. An isolation technique termed LOCOS (for LOCalized Oxidation of Silicon) involves the thermal growth of recessed field oxides in field regions between adjacent IGFETs. Prior to growing the field oxides, a thin layer of silicon nitride covers the active regions and exposes the field regions, and ion implantation provides a channel-stop implant that is self-aligned to the field regions. The channel-stop implant increases doping under the field oxides to ensure the threshold voltage of parasitic devices is greater than any operating voltage. Thick field oxides render the channel-stop implant unnecessary, but are generally not used to reduce step coverage problems. For submicron IGFETs, LOCOS-based techniques are often replaced by trench-based isolation schemes. For instance, with shallow trench and refill isolation, a trench on the order of 3000 to 5000 angstroms deep is anisotropically etched into the silicon substrate, a short thermal oxidation is applied to control the interface quality on the trench walls, an insulative material is filled into the trench, and the surface is planarized using chemical-mechanical polishing. Deep trench isolation is also known in the art. Trench-based isolation provides smaller isolation spacing than is possible with LOCOS. In addition, the fully recessed structure provides a planar top surface, and the sharp lower comers provide improved isolation efficiency due to the so called "corner effect." A drawback to trench-based isolation, however, is the need for additional processing steps dedicated solely to forming the trenches.
Accordingly, a need exists for an IGFET that can be manufactured with reduced horizontal dimensions and a substantially planar top surface in conjunction with an efficient technique for providing device isolation. It is especially desirable that the IGFET have a channel length that can be significantly smaller than the minimum resolution of the available lithographic system.